This invention relates to communications, and more particularly to a high data rate spread-spectrum system.
In a fixed bandwidth CDMA system, increasing the data rate reduces the processing gain. To maintain a high data rate, the prior art teaches the transmission of spread-spectrum signals with parallel orthogonal chip-sequence signals. The use of parallel chip-sequence signals, however, results in increased interference in the receiver due to multipath. In addition, when transmitting parallel chip-sequence signals, the transmitted output signal usually is distorted as a result of nonlinearities in the output amplifiers and filters.
FIGS. 1 and 2 show a prior art spread-spectrum system, transmitting data at high processing gain. The example is for an encoded data rate of 100 megabits per second (Mb/s), although any data rate could be used. The data are demultiplexed by demultiplexer 45 into four data streams, each with a symbol rate of 25 mega-symbols/second. Four product devices 41, 42, 443, multiply the four data streams by four orthogonal chip-sequence signals g1(t), . . . , g4(t), from chip-sequence generator 44, which have a chip rate of 400 mega-chips/second. The four chip-sequence signals could be sent as five-level pulse amplitude modulation (PAM), by multiplying by cos xcfx890t or as three amplitudes in each of cos xcfx890t and sin xcfx890t axes. The outputs from the product devices 41, 42, 443 are combined by combiner 46, and transmitted as a radio wave, at a carrier frequency xcfx890, over a communications channel. Signal source 16 and product device 15 translate the output from combiner 46 to the carrier frequency, using a standard up-converter device. The antenna 17 is coupled to the radio wave to the communications channel.
The receiver has four matched filters 711, 712, 714 for detecting the four parallel signals. At the receiver, antenna 24, product device 25 and receiver signal source 26 receive and translate the multichannel spread-spectrum signal to a processing frequency. The multiplexer 54 multiplexes the outputs from the matched filters 711, 712, 714. De-interleaver 37 de-interleaves the multiplexed data, and FEC decoder 38 decodes the de-interleaved data as estimated data.
Multipath causes delayed versions of g1(t), g2(t), g3(t) and g4(t) to be present at each matched filter. Consider the first matched filter 711. The delayed versions are not orthogonal to the first chip-sequence signal g1(t) and multipath interference results. The number of interferers is due to the number of parallel codes, number of simultaneous users, etc.
Further, any multipath signals can be generated by each of the multilevel pulse amplitude modulation signals, which can produce one of M levels for each chip. The number of levels produced is M. This large variation in amplitude results in distortion due to filtering and to nonlinearities in the transmit output amplifier.
A general object of the invention is to facilitate the transmission and reception of a high data rate signal using a high processing gain CDMA system without using parallel codes.
A second object is the efficient acquisition and synchronization of such a signal.
According to the present invention, as embodied and broadly described herein, an improvement to a spread-spectrum system is provided for sending data over a communications channel. The spread-spectrum system is assumed to handle high data rate communications. The improvement includes, at the transmitter, a memory which typically is coupled to a bit interleaver, and a chip-sequence encoder, which is coupled to the memory and to a transmitter section. At the receiver, the improvement includes a plurality of product devices, a plurality of integrators, a comparator, and a chip-sequence-signal generator and controller.
At the transmitter, the memory stores N bits of interleaved data, or other data, from an interleaver, or other data source, respectively. The chip-sequence encoder uses the N bits of stored data for selecting one of 2N orthogonal chip-sequence signals stored in the chip-sequence encoder. The chip-sequence encoder outputs the selected chip-sequence signal. The number of bits, N, is the number of bits in a symbol, used for selecting one of the 2N chip-sequence signals. While orthogonal signals are preferred, near-orthogonal signals also can be employed, albeit at the cost of a slightly higher error rate.
At the receiver, at the processing frequency, 2N correlators are employed, one for each of the 2N possible signals. The outputs from the 2N correlators are compared, and the output with the largest value is chosen. 2N matched filters also could be employed, however, using matched filters is not a preferred approach since 2N matched filters would require more gates, and therefore more cost.
For acquisition, the 2N product devices multiplies the received header of the spread-spectrum signal by a replica of the header signal, which is stored or generated at the receiver, and which typically is taken from the plurality of 2N chip-sequence signals. Each correlator is delayed, one from the other, by one-half chip in a preferred system. The chip-sequence signal has the first chip-sequence signal, and has a delay of at least one chip with respect to each chip-sequence signal from the plurality of 2N chip-sequence signals. Each chip-sequence signal has a different delay from other chip-sequence signals from the plurality of 2N chip-sequence signals. Timing is obtained by using the timing of the correlator with the largest output.
The plurality of product devices, after acquisition, multiplies the received spread-spectrum signal by the plurality of 2N chip-sequence signals, with each chip-sequence signal from the plurality of 2N chip-sequence signals having a different chip-sequence signal from other chip-sequence signals from the plurality of 2N chip-sequence signals. The plurality of integrators are coupled to the plurality of product devices, respectively. The plurality of integrators integrate a plurality of products from the plurality of product devices during the period of a chip-sequence signal. The comparator, which is coupled to the plurality of integrators, selects a largest value from the plurality of integrators. The chip-sequence decoder decodes the largest value from a respective integrator of the plurality of integrators into N bits of data or interleaved data, depending on the originating source at the transmitter.
Additional objects and advantages of the invention are set forth in part in the description which follows, and in part are obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention also may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.